The present invention generally relates to optical and process correction (OPC) in photolithography, and more specifically relates to a method and system for utilizing simplified resist process models to perform optical and process corrections.
Making a semiconductor device, such as an integrated circuit (IC), involves using photolithography to form patterns on a wafer, where the patterns correspond to complex circuitry. During the process, the patterns are initially formed on a reticle or mask, and then the patterns are exposed on the wafer by shining a light through, or illuminating, the mask.
During the optical lithography step in integrated circuit fabrication, a device structure is patterned by imaging a mask onto a radiation sensitive film (photoresist or resist) coating different thin film materials on the wafer. These photoresist films capture the pattern delineated through initial exposure to radiation and allow subsequent pattern transfer to the underlying layers. During exposure, depth of focus (DOF) indicates the range of distances around a focal plane where the image quality is sharp. It is important to optimize the illumination of a mask to achieve maximum common DOF, as this results in the best exposure of the wafer. The radiation source, imaging optics, mask type and resist performance determine the minimum feature size that can be reproduced by the lithography process. Imaging of mask patterns with critical dimensions smaller than the exposure wavelength results in distorted images of the original layout pattern, primarily because of optical proximity effects of the imaging optics. Nonlinear response of the photoresist to variability in exposure tool and mask manufacturing process as well as variability in resist and thin film processes also contribute to image distortion. These distortions include variations in the line-widths of identically drawn features in dense and isolated environments (iso-dense bias), line-end pullback or line-end shortening from drawn positions and corner rounding.
Mask error factor limits the amount of a common process window which is useable. Optical Proximity Correction or Optical and Process Correction (OPC) is common in the industry and involves the pre-compensation of predicted defects of a circuit design. OPC is a procedure of pre-distorting the mask layout by using simple shape manipulation rules (rule-based OPC) or fragmenting the original polygon into line segments and moving these segments to favorable positions as determined by a process model (model-based OPC). Using OPC improves image fidelity on a wafer. As the semiconductor industry pushes to resolve smaller critical dimensions, the need to provide more accurate OPC modeling becomes critical.
Deep ultra-violet (DUV) lithography normally uses chemically amplified (CA) resists. These systems contain a photoacid generator compound that decomposes when exposed to light. While a post exposure bake (PEB) step is not required for processes in which a soft resist is desired (e.g., metal liftoff patterning), a post exposure bake is needed for acid etching, e.g. BOE. Post exposure bake also introduces some stress into the photoresist. Additionally, some shrinkage of the photoresist may occur. During post exposure bake (PEB), the acid decomposition product induces a cascade of chemical transformations, changing the solubility of exposed regions.
Because the post exposure bake process effects the resist, it must can taken into account in advance when performing OPC. There are CA photoresist process modeling accuracy issues for OPC applications. One current approach includes diffused aerial image modeling. However, typically the photoresist process exhibits non-linear reaction/diffusion mechanisms that diffused aerial image models cannot simulate. Another approach includes variable threshold modeling, but this requires a large set of data for calibration. Still another approach includes using full resist process models. However, full physical resist process model calculations are generally too slow for OPC calculations.